
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Pulse-Width Modulation Generators
Table 30. PWM Timing 1
Parameter
Min
Max
Unit
Switching Characteristics
t PWMW
t PWMP
PWM Output Pulse Width
PWM Output Period
t PCLK – 2
2 × t PCLK – 1.5
(2 16 – 2) × t PCLK
(2 16 – 1) × t PCLK
ns
ns
1
Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).
t PWMW
PWM
OUTPUTS
t PWMP
Figure 26. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 31 are valid at the DAI_P20–1 pins. This feature is not
available on the ADSP-21363 models.
Table 31. SRC, Serial Input Port
Parameter
Timing Requirements
Min
Unit
t SRCSFS 1
t SRCHFS 1
t SRCSD 1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
SDATA Setup Before Serial Clock Rising Edge
3
3
3
ns
ns
ns
t SRCHD
1
SDATA Hold After Serial Clock Rising Edge
3
ns
t SRCCLKW
t SRCCLK
Clock Width
Clock Period
36
80
ns
ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s
input can be either CLKIN or any of the DAI pins.
Rev. J |
Page 35 of 60 |
July 2013